Glossary

One or two lines per term. Where a term has a course lesson that owns it, the lesson title is given so you know where to read more.

A

• AAPCS: Arm Architecture Procedure Call Standard. Arguments in r0-r3, return value in r0, r4-r11 preserved by the callee, 8-byte stack alignment at calls. See Functions and the Calling Convention.
• ABI: Application Binary Interface. The rules for calling functions, laying out data, and naming symbols that let separately compiled code link and run together.
• Active object: A design pattern combining a private event queue, a state machine, and a thread or priority level; objects communicate only by posting events.
• ADC: Analog-to-digital converter. Samples a voltage and returns a number; the STM32F407 has three 12-bit ADCs.
• AHB: Advanced High-performance Bus. Arm’s high-speed on-chip bus; on the STM32F407 the GPIO ports, RCC, and DMA sit on AHB1 at the full system clock.
• Alignment: The requirement that an object’s address be a multiple of some power of two, usually its size. Cortex-M4 tolerates unaligned single loads and stores, but not unaligned multiple-register or exclusive accesses.
• Alternate function (AF): A GPIO mode where a peripheral such as a UART drives the pin. Selected per pin in AFRL/AFRH; USART2 on PA2/PA3 is AF7.
• APB: Advanced Peripheral Bus. A slower, simpler bus bridged from AHB; on the STM32F407 APB1 runs at up to 42 MHz and APB2 at up to 84 MHz.
• Arena allocator: Allocates by bumping a pointer through a fixed buffer and frees everything at once. Deterministic and fragmentation-free.
• ART Accelerator: ST’s instruction prefetch queue and caches in front of flash on the STM32F4, which hides most of the flash wait states at 168 MHz.
• Atomic operation: An operation that other code (an interrupt, another core) can never observe half-done. On Cortex-M, aligned 8, 16, and 32-bit loads and stores are atomic; i++ is not.

B

• Bare metal: Firmware that runs directly on the hardware with no operating system underneath.
• Barrier: An instruction that enforces ordering of memory accesses or instruction fetches: DMB, DSB, ISB. A compiler barrier ("memory" clobber) only stops the compiler from reordering.
• BASEPRI: Cortex-M special register that masks all interrupts at or below a given priority while leaving more urgent ones enabled. Used by RTOS critical sections.
• Baud rate: Symbols per second on a serial line; for UART, bits per second including start and stop bits.
• Bit-banding: A Cortex-M3/M4 feature that maps each bit of a region of SRAM or peripheral space to its own word in an alias region, so a single store sets or clears one bit atomically.
• Bitfield: A struct member with an explicit width in bits. Layout is implementation-defined, so firmware usually prefers masks and shifts for registers.
• BOR: Brown-out reset. Holds the chip in reset while the supply voltage is below a threshold, preventing erratic execution as the battery sags.
• Bootloader: A small program that runs first after reset and decides what to run next: validates and jumps to the application, or receives a firmware update. See Bootloaders and Firmware Update.
• BSP: Board support package. The code and configuration specific to one board: pin assignments, clock setup, which UART is the console.
• BSRR: GPIO bit set/reset register on STM32. Writing 1 to bit n sets pin n, writing 1 to bit n+16 clears it, in one atomic write with no read-modify-write.
• bss section: Statically allocated variables with no initialiser or a zero initialiser. Occupies RAM but no flash; startup code zeroes it.
• Bus fault: A Cortex-M exception raised when a memory access gets an error response, for example an access to an unmapped address.
• Bus matrix: The interconnect inside the chip that routes transactions from bus masters (CPU, DMA) to slaves (flash, SRAM, peripherals).

C

• CAN: Controller Area Network. A differential, multi-master bus with priority arbitration by message ID, standard in vehicles and industrial equipment.
• CCM RAM: Core-coupled memory. 64 KB of RAM at 0x10000000 on the STM32F407, reachable only by the CPU’s data bus: fast, but not usable for DMA or code.
• Circular buffer: See Ring buffer.
• Clock gating: Turning off the clock to an unused peripheral to save power. On STM32 every peripheral starts gated; you enable it in RCC.
• Clock tree: The network of oscillators, PLLs, multiplexers, and prescalers that generates every clock in the chip from a few sources.
• CMSIS: Cortex Microcontroller Software Interface Standard. Arm’s vendor-neutral headers and functions for core features (NVIC_EnableIRQ, __DSB), plus libraries such as CMSIS-DSP.
• COBS: Consistent Overhead Byte Stuffing. Encodes a packet so it contains no zero bytes, letting 0x00 act as an unambiguous frame delimiter at the cost of at most one byte per 254.
• Context switch: Saving one task’s registers and stack pointer and restoring another’s. On Cortex-M it is normally done in the PendSV handler.
• Cortex-M: Arm’s family of microcontroller CPU cores (M0, M0+, M3, M4, M7, M23, M33, M55, M85), licensed to chip vendors.
• CPOL/CPHA: SPI clock polarity and phase. Their four combinations are SPI modes 0 to 3 and must match the device.
• CRC: Cyclic redundancy check. A checksum computed by polynomial division, good at detecting accidental corruption but useless against deliberate tampering.
• Critical section: Code that must run without interruption by code that shares the same data, typically protected by masking interrupts or taking a mutex.
• Cross compiler: A compiler that runs on one architecture and generates code for another, such as arm-none-eabi-gcc on an x86 PC.
• CYCCNT: The DWT cycle counter at 0xE0001004, a 32-bit register that counts CPU clock cycles. Ideal for measuring execution time.

D

• DAC: Digital-to-analog converter. Outputs a voltage proportional to a number.
• Data race: Two accesses to the same memory location from concurrent contexts, at least one a write, with no synchronisation. Undefined behaviour in C11 threads; a real bug with ISRs.
• data section: Statically allocated variables with a non-zero initialiser. Lives in RAM at run time, with the initial values stored in flash and copied by startup code.
• Datasheet: The chip’s electrical and pinout document: voltages, currents, timing, package. Register details live in the reference manual.
• Debouncing: Filtering the rapid on/off bouncing of a mechanical switch so one press registers once.
• Debug probe: Hardware that connects a PC to a chip’s debug port, such as ST-Link, J-Link, or a CMSIS-DAP adapter.
• Device tree: A data structure describing hardware (addresses, interrupts, pins) used by Linux and Zephyr instead of hard-coded register headers.
• DMA: Direct memory access. A controller that moves data between peripherals and memory without the CPU. See DMA.
• Duty cycle: The fraction of a PWM period during which the output is high.
• DWT: Data Watchpoint and Trace unit. Cortex-M debug block providing watchpoint comparators and the cycle counter.

E

• EABI: Embedded ABI. The Arm ABI variant used by bare-metal and embedded toolchains, hence the eabi in arm-none-eabi.
• EEPROM: Electrically erasable programmable ROM. Non-volatile memory that can be rewritten byte by byte; external chips are common for small, frequently changed data.
• EEPROM emulation: Storing small records in flash with an append-only log and periodic compaction, to give EEPROM-like behaviour on a chip that has only flash.
• ELF: Executable and Linkable Format. The file format for object files and linked executables; contains sections, symbols, and debug information.
• Endianness: Byte order of multi-byte values in memory. Little-endian stores the least significant byte at the lowest address; Cortex-M is little-endian.
• Errata: The vendor’s published list of known silicon bugs and workarounds for a chip. Read it before trusting a peripheral.
• EXC_RETURN: The special value placed in lr on exception entry, such as 0xFFFFFFF9. Branching to it returns from the exception and tells the core which stack and frame type to restore.
• Exception: Any event that makes the Cortex-M core leave normal flow and run a handler from the vector table: reset, faults, SVC, PendSV, SysTick, and interrupts.
• EXTI: Extended interrupts and events controller on STM32. Turns edges on GPIO pins (and some internal events) into interrupt requests.

F

• FAULTMASK: Cortex-M special register that, when set, masks every exception except NMI, including HardFault.
• Fixed-point: Representing fractional numbers as scaled integers, such as Q15 or millivolts in an int32_t. Fast and deterministic on MCUs without double-precision hardware.
• Flash memory: Non-volatile memory that holds the firmware. Erased in large sectors to all 1s, programmed by turning 1s into 0s, with limited erase cycles.
• Flash wait states: Extra CPU cycles inserted on each flash read because flash is slower than the core; 5 on the STM32F407 at 168 MHz.
• FPU: Floating-point unit. The Cortex-M4F has a single-precision FPU; double math is done in software.
• Freestanding: A C implementation that guarantees only a minimal library (stddef.h, stdint.h, and a few others). Bare-metal firmware is freestanding in principle, though most toolchains supply newlib.
• FreeRTOS: The most widely used open-source RTOS for microcontrollers: tasks, queues, semaphores, timers, in a few kilobytes.
• Full duplex: Data flows in both directions at the same time, as in SPI and UART with separate TX and RX lines.

G

• GDB: The GNU debugger. Talks to a target through a gdb server such as OpenOCD.
• gdb server: A program that speaks gdb’s remote serial protocol on a TCP port and translates it to debug probe operations; OpenOCD listens on port 3333.
• GPIO: General-purpose input/output. A pin whose direction and level software controls. See GPIO in Depth.
• Guard region: A memory area that must never be accessed, placed below a stack so an overflow causes a fault instead of silent corruption. Implemented with the MPU.

H

• HAL: Hardware abstraction layer. A software layer that hides register details behind functions; also the name of ST’s vendor library.
• Half duplex: Data flows in both directions, but only one at a time, as in I2C and RS-485.
• HardFault: The catch-all Cortex-M fault exception, raised for faults that are not handled by a more specific handler or that happen during exception processing.
• Harvard architecture: Separate buses for instructions and data. Cortex-M3/M4 use separate instruction and data buses for code memory, allowing simultaneous fetch and data access.
• Heap: Memory managed at run time by malloc and free. Firmware often avoids it because of fragmentation and non-deterministic timing.
• HIL: Hardware-in-the-loop testing. Running automated tests on real hardware driven and measured by a test host.
• HSE: High-speed external oscillator. A crystal or external clock, 8 MHz on the STM32F4 Discovery; accurate enough for USB and precise UART timing.
• HSI: High-speed internal oscillator. The 16 MHz RC oscillator the STM32F407 runs from after reset; convenient but only about 1% accurate.

I

• I2C: Inter-Integrated Circuit. A two-wire, open-drain, half-duplex bus (SCL, SDA) with 7-bit device addresses. See SPI and I2C.
• Idle task: The lowest-priority RTOS task, run when nothing else is ready; usually executes WFI to save power.
• Implementation-defined behaviour: Behaviour the C standard leaves to the compiler, which must document its choice: size of int, signedness of char, right shift of negative numbers.
• Inline assembly: Assembly embedded in C with __asm volatile(...), used for special instructions and registers.
• Input capture: A timer mode that records the counter value when an input edge arrives, for measuring pulse widths and frequencies.
• Interrupt: A hardware request that diverts the CPU to a handler between instructions. See Interrupts Done Right.
• Interrupt latency: The time from an interrupt request to the first instruction of its handler; 12 cycles on Cortex-M4 in the best case.
• IRQ: Interrupt request. Also the device interrupt number (IRQn) used to index the NVIC, such as USART2 = 38 on the STM32F407.
• ISR: Interrupt service routine, the handler function for an interrupt.
• ITM: Instrumentation Trace Macrocell. Cortex-M debug block that sends software messages (such as printf output) through the SWO pin with little CPU overhead.
• IWDG: Independent watchdog on STM32, clocked by the LSI so it keeps running even if the main clock fails.

J

• JTAG: An older, four-to-five-wire debug and boundary-scan interface. Cortex-M parts usually support both JTAG and the two-wire SWD.

K

• Kconfig: The configuration language from the Linux kernel, also used by Zephyr, to select features and set compile-time options.

L

• Late arrival: A Cortex-M optimisation where a higher-priority interrupt that arrives during stacking for a lower one is serviced first, reusing the stacked frame.
• Lazy stacking: Cortex-M4F reserves space for FPU registers on exception entry but saves them only if the handler uses the FPU, cutting latency.
• Linker: The tool that combines object files and libraries, resolves symbols, and assigns final addresses according to a linker script.
• Linker script: A file (.ld) that tells the linker where memory regions are and which sections go where. See Linker Scripts.
• Literal pool: Constants stored in flash next to the code that uses them, loaded with PC-relative ldr. This is how ldr r0, =0x40020C00 works.
• LittleFS: A small, power-loss resilient, wear-levelling filesystem designed for microcontroller flash.
• LMA: Load memory address. Where a section’s bytes are stored in the image (flash). Compare VMA.
• Lock-free: An algorithm where shared data is updated with atomic operations instead of locks, so a stalled context cannot block others.
• LSE / LSI: Low-speed external (32.768 kHz crystal) and low-speed internal (about 32 kHz RC) oscillators, used for the RTC and the independent watchdog.
• LTO: Link-time optimisation. The compiler optimises across all translation units at link time; enabled with -flto.

M

• Map file: A linker-generated text file listing every section and symbol with its address and size. The first place to look when flash or RAM is full.
• MCU: Microcontroller unit. A chip with CPU, flash, RAM, and peripherals together, running code directly from on-chip memory.
• MCUboot: An open-source secure bootloader for microcontrollers, supporting signed images, multiple slots, and swap-based updates.
• Memory-mapped I/O: Peripheral registers that appear at addresses in the normal address space, accessed with ordinary loads and stores.
• Memory pool: An allocator that hands out fixed-size blocks from a static array. Constant-time and fragmentation-free.
• MISRA C: A set of C coding guidelines for safety-related systems that restricts features prone to undefined or surprising behaviour.
• MMU: Memory management unit. Translates virtual to physical addresses and isolates processes. MPUs (microprocessors) have one; Cortex-M does not.
• MPU (memory protection unit): Optional Cortex-M block that sets access permissions and attributes on up to 8 or 16 address regions, without address translation. See Memory Protection, Stack Safety, and Robustness.
• MPU (microprocessor unit): A processor that relies on external memory and usually has an MMU, typically running Linux. Context tells you which MPU is meant.
• MSP: Main stack pointer. Used after reset, by all exception handlers, and by Thread mode unless switched to PSP.
• Mutex: A lock with an owner, used to serialise access to a shared resource between tasks. RTOS mutexes usually implement priority inheritance.

N

• Newlib: The C standard library shipped with the GNU Arm toolchain.
• newlib-nano: A size-optimised build of newlib, selected with --specs=nano.specs; its printf omits floating point unless requested.
• NMI: Non-maskable interrupt. Exception 2, which cannot be disabled by PRIMASK; on STM32 it is raised by the clock security system.
• noinit section: A RAM section that startup code neither initialises nor zeroes, so its contents survive a warm reset. Used for crash records and boot flags.
• NOR flash: The flash technology used for MCU program memory and SPI flash chips: random-access reads, can execute in place, erased in sectors.
• NVIC: Nested Vectored Interrupt Controller. The Cortex-M block that enables, prioritises, and dispatches interrupts.

O

• Object file: The output of compiling one source file (.o): machine code and data in sections, plus a symbol table, with addresses not yet final.
• Open-drain: An output that can only pull low; a pull-up resistor provides the high level. Required for I2C and wired-OR signals.
• OpenOCD: Open On-Chip Debugger. Drives debug probes, flashes chips, and provides a gdb server.
• Option bytes: Non-volatile configuration bits on STM32 such as read protection level, brown-out level, and watchdog behaviour.
• OTA: Over-the-air update. Delivering new firmware through a radio or network link.
• OTP: One-time programmable memory. Bits can be written once and never erased; used for serial numbers and keys.
• Output compare: A timer mode that changes an output pin or raises an interrupt when the counter matches a compare register.
• Oversampling: Taking several ADC samples and averaging or summing them to reduce noise or gain effective resolution.

P

• Peripheral: An on-chip hardware block other than the CPU and memory: GPIO, UART, timers, ADC, DMA.
• PendSV: Pendable service call. A software-triggered exception, usually at the lowest priority, used by RTOSes to perform context switches.
• PLL: Phase-locked loop. A circuit that multiplies a reference clock; the STM32F407 uses one to reach 168 MHz from an 8 MHz crystal.
• Polling: Repeatedly reading a status register in a loop until a condition is true, instead of waiting for an interrupt.
• Preemption: A higher-priority interrupt or task interrupting a lower-priority one that is already running.
• Prescaler: A clock divider in front of a peripheral or timer.
• Priority inversion: A high-priority task waits for a lock held by a low-priority task, which is itself preempted by a medium-priority task. Fixed by priority inheritance or ceiling protocols.
• PRIMASK: Cortex-M special register that, when set, masks all configurable-priority exceptions. Set by cpsid i / __disable_irq().
• Privileged mode: The execution level that can access all registers and memory. Handlers always run privileged; Thread mode can be dropped to unprivileged.
• PSP: Process stack pointer. The alternate stack pointer used by RTOS tasks in Thread mode.
• Pull-up / pull-down: A resistor that holds a line high or low when nothing drives it. STM32 GPIO has internal ones of about 40 kOhm.
• Push-pull: An output that actively drives both high and low.
• PWM: Pulse-width modulation. A fixed-frequency square wave whose duty cycle encodes a value, used for LED dimming, motor control, and servos.

Q

• QEMU: An open-source machine emulator; in this course used with -M netduinoplus2 to run STM32F405 firmware.
• QSPI: Quad SPI. SPI with four data lines, used for fast external flash, often memory-mapped for execute-in-place.
• Queue: An RTOS object that passes copies of fixed-size messages between tasks or from ISRs to tasks, with blocking and timeouts.

R

• RCC: Reset and clock control. The STM32 peripheral that configures oscillators, the PLL, bus prescalers, and per-peripheral clock enables. Base 0x40023800.
• RDP: Readout protection. STM32 option byte setting that blocks debug access to flash: level 0 none, level 1 reversible with a mass erase, level 2 permanent.
• Read-modify-write: Reading a register, changing some bits, writing it back. Not atomic: an interrupt in between can lose an update.
• Reentrant: A function that works correctly if called again before a previous call finishes, for example from an ISR. Requires no unprotected static state.
• Reference manual: The vendor’s full description of a chip family’s peripherals and registers; RM0090 for the STM32F407.
• Register: Either a storage slot inside the CPU core (r0-r15) or a memory-mapped control word in a peripheral. Context tells you which.
• Renode: An open-source simulator from Antmicro that models complete boards, including the STM32F4 Discovery, and supports scripted testing.
• Reset handler: The function whose address is in vector table entry 1; the first code to run after reset.
• Ring buffer: A fixed-size array used as a FIFO with wrapping head and tail indices. With one producer and one consumer it needs no lock.
• rodata section: Read-only data such as const tables and string literals, placed in flash.
• RTC: Real-time clock. A low-power counter, usually clocked from a 32.768 kHz crystal, that keeps time and can wake the chip.
• RTOS: Real-time operating system. A small kernel providing tasks, scheduling, and synchronisation with bounded timing. See RTOS Fundamentals.
• RTT: SEGGER Real-Time Transfer. Fast logging through ring buffers in target RAM that the debug probe reads in the background.

S

• Schmitt trigger: An input circuit with hysteresis that turns a slow or noisy edge into a clean transition.
• Secure boot: Verifying a cryptographic signature on each firmware stage before running it, from an immutable root of trust.
• Section: A named block of code or data in an object file (.text, .data, .bss) that the linker places as a unit.
• Semaphore: A counter used for signalling between contexts (binary semaphore) or tracking available resources (counting semaphore). Has no owner.
• Semihosting: A debug mechanism where the target uses the host’s console and files through the debugger by executing bkpt 0xAB. Very slow, and it causes a HardFault if no debugger is attached.
• Sleep mode: A low-power state entered with WFI or WFE where the CPU clock stops but peripherals keep running.
• SPI: Serial Peripheral Interface. A four-wire synchronous, full-duplex bus (SCK, MOSI, MISO, CS) with one master.
• Stack: The region of RAM holding function frames: locals, saved registers, return addresses. Grows downward on Cortex-M.
• Stack overflow: The stack growing past its allocated region into other data. On an MCU without an MPU guard it corrupts memory silently.
• Stack painting: Filling the stack with a known pattern at startup, then checking how much was overwritten to find peak usage (the high-water mark).
• Startup code: Code that runs between reset and main: sets up the vector table, copies .data, zeroes .bss, enables the FPU, calls main.
• Superloop: A firmware structure of initialisation followed by one infinite loop that polls and services everything in turn.
• SVC: Supervisor call. The svc instruction raises the SVCall exception; used for system calls from unprivileged code and to start the first RTOS task.
• SVD: System View Description. An XML file describing every peripheral register and bit field of a chip, used by debuggers and code generators.
• SWD: Serial Wire Debug. Arm’s two-wire debug interface (SWDIO, SWCLK); on the STM32F407 the pins are PA13 and PA14.
• SWO: Serial Wire Output. A single trace pin carrying ITM data to the debug probe.
• System clock (SYSCLK): The main clock feeding the CPU and AHB bus, selected from HSI, HSE, or PLL.
• SysTick: A 24-bit down-counting timer built into every Cortex-M core, typically configured for a 1 ms system tick.

T

• Tail chaining: When one exception handler ends while another is pending, Cortex-M skips the unstack and restack and jumps straight to the next handler.
• TCB: Task control block. The RTOS data structure for a task: saved stack pointer, priority, state, and bookkeeping.
• text section: Executable code, placed in flash.
• Thumb-2: The Arm instruction set used by Cortex-M, mixing 16-bit and 32-bit instructions.
• Tick: The periodic interrupt that drives an RTOS’s or application’s notion of time, usually 1 ms from SysTick.
• Tickless idle: An RTOS power-saving mode that stops the periodic tick while idle and wakes from a low-power timer at the next needed time.
• Timer: A peripheral with a counter, prescaler, and compare/capture channels, used for periodic interrupts, PWM, and measurement. See Timers and PWM.
• TrustZone: The ARMv8-M security extension (Cortex-M23/M33 and later) that splits the chip into secure and non-secure worlds.
• Two’s complement: The representation of signed integers used by every modern CPU: negate by inverting all bits and adding one.

U

• UART: Universal asynchronous receiver/transmitter. Serial communication with start and stop bits and no shared clock. See UART: Serial Communication.
• Unaligned access: Accessing a multi-byte value at an address that is not a multiple of its size. Allowed for some instructions on Cortex-M4, faults on Cortex-M0, and undefined behaviour in C through a typed pointer.
• Undefined behaviour (UB): Code for which the C standard imposes no requirements, such as signed overflow or out-of-bounds access. The optimiser assumes it never happens.
• USART: Universal synchronous/asynchronous receiver/transmitter. ST’s UART peripheral, which can also run in synchronous mode.
• USB: Universal Serial Bus. A host-controlled bus with enumeration, endpoints, and device classes; the STM32F407 has full-speed and high-speed OTG controllers.

V

• Vector table: The table of the initial stack pointer and exception handler addresses at the start of the image, read by the core at reset and on every exception.
• VMA: Virtual memory address. On an MCU, the address where a section lives at run time. For .data the VMA is in RAM while the LMA is in flash.
• volatile: A C qualifier that makes every access to an object a side effect the compiler must perform as written. Required for hardware registers; not atomic and not a barrier.
• Voltage scaling: Lowering the core regulator’s output voltage to save power at reduced maximum frequency.
• VTOR: Vector table offset register at 0xE000ED08. Relocates the vector table, as bootloaders do before jumping to an application.

W

• Watchdog: A hardware timer that resets the chip unless software refreshes it in time, recovering from hangs. See Watchdogs, Faults, and Recovering From Them.
• Watchpoint: A debugger feature that halts the core when a given address is read or written; the Cortex-M4 has four.
• Weak symbol: A symbol defined with __attribute__((weak)) that is used only if no strong definition exists. Default interrupt handlers are weak so you can override them by name.
• WFI / WFE: Wait for interrupt / wait for event. Instructions that stop the CPU clock until something happens.
• Write-1-to-clear (W1C): A register bit that is cleared by writing 1 to it; writing 0 has no effect. Common for interrupt and fault status flags.
• WWDG: Window watchdog on STM32. Resets the chip if refreshed too late or too early.

X

• XIP: Execute in place. Running code directly from flash (internal or memory-mapped QSPI) without copying it to RAM first.
• XN: Execute never. A memory attribute that faults any instruction fetch from the region, set through the MPU or by the default memory map.

Z

• Zephyr: A Linux Foundation open-source RTOS with a device tree, Kconfig, a large driver set, and networking and Bluetooth stacks.
• Zero-copy: Passing data by reference (pointer and length, or buffer ownership) instead of copying it between layers.